1. Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to the formation of self-aligned dual damascene interconnects and vias, which incorporates two positive photoresist systems, which have different wavelength sensitivities, to form trench/via openings with only a two-step etching process.
2. Description of Related Art
It remains a challenge in dual damascene processing to develop simplified processing with fewer processing steps, both photo and etch steps, to achieve the trench/via patterning and formation of trench and via openings.
As a background to the current invention, the damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide reactive ion etch (RIE), then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices.
Key to the damascene processing approach is that the deposited conductive metal is deposited into a previously deposited patterned insulator. This is desirable because mask alignment, dimensional control, rework, and the etching process are all easier when applied to a dielectric rather than metal films. Damascene processing achieves these benefits by shifting the enhanced filling and planarization requirements from dielectric to metal films, and by shifting control over interconnect thickness from metal deposition to insulator patterning and metal chem-mech polishing.
The related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,877,076 entitled “Opposed Two-Layered Photoresist Process for Dual Damascene Patterning” granted Mar. 2, 1999 to Dai teaches a dual damascene photo process using two photoresist layers with opposite types, one positive and one negative, photo sensitivities and a two-step exposure. A layer of positive type chemical amplification resist is deposited over the composite dielectric layer. The resist is next trench line patterned by exposing and developing it through a dark field mask. This is followed by cross-linking the remaining resist by performing a hard-bake. A negative type resist is formed over the positive resist, and contact via hole patterned through a clear field mask. Patterns are transferred in the underlying dielectrics by etching, to form trench line and contact via hole openings for dual damascene processing.
U.S. Pat. No. 5,877,075 entitled “Dual Damascene Process Using Single Photoresist Process” granted Mar. 2, 1999 to Dai et al. describes a dual damascene process using a silylation process with a single photoresist process and a two-step exposure. A substrate is provided with a tri-layer of insulation formed thereon. A layer of photoresist is formed on the substrate and is imaged with a hole pattern by exposure through a dark field mask. Hole is formed in the photoresist by a wet etch. As a key step, the photoresist is next subjected to post-exposure bake such that the sensitivity of the photoresist is still retained. The same photoresist layer is then exposed for the second time for aligned line patterning using a “clear-field” mask. The line patterned region is cross-linked by performing pre-silylation bake, which region in turn is not affected by the subsequent silylation process that forms a silicon rich mask in the field surrounding the hole and line patterns. Through a series of process steps, hole and line patterns are formed in the insulation layer, and metal is deposited in a dual damascene process.
U.S. Pat. No. 5,882,996 entitled “Method of Self-Aligned Dual Damascene Patterning Using Developer Soluble ARC Interstitial Layer” granted Mar. 16, 1999 to Dai describes a method for patterning dual damascene interconnections in semiconductor chips through the use of a developer soluble ARC interstitial layer. This is accomplished by providing a silicon substrate having a composite layer of insulation deposited thereon whereby said composite layer comprises a first layer of dielectric separated from a second layer of dielectric by an intervening intermediate layer of silicon nitride. Then, two layers of photoresist are deposited with an intervening interstitial layer of water soluble anti-reflective coating (ARC). The ARC, having a relatively high refractive index, serves as a barrier to light so that the top layer of photoresist is first line patterned without affecting the second layer. The second layer of photoresist is next hole patterned. The hole pattern is transferred into the top dielectric layer and the intervening silicon nitride layer by etching. The line pattern in the first photoresist layer is etched into the top dielectric layer at the same time the hole pattern is transferred from the top dielectric layer into the bottom dielectric layer by the same etching process. The photoresist layers are then removed and the dual damascene structure formed is filled with metal forming the metal line and hole interconnection on the semiconductor substrate.
U.S. Pat. No. 5,906,911 entitled “Process of Forming a Dual Damascene Structure in a Single Photoresist Film” granted May 25, 1999 to Cote describes a dual damascene process using just one single layer of photoresist with two photomasks and selective silylation. The process includes the steps of forming a photoresist film on a substrate, pattern exposing the photoresist film to form a first pattern in the photoresist film, and forming an etch resistant layer in the first pattern. The photoresist film is pattern exposed a second time to form a second pattern in the photoresist film. After several more process steps and etching, dual damascene trench and via opens are formed.
U.S. Pat. No. 5,936,707 entitled “Multi-Level Reticle System and Method for Forming Multi-Level Resist Profiles” granted Aug. 10, 1999 to Nguyen et al. teaches a dual damascene photo process using single photoresist process. A method is described for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thickness in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multilevel resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.